Since a system LSI device has a lot of system function devices formed on a same single chip and an SoC (system-on-chip) device has memories, logic circuits and analog circuits integrated in a chip, such a system LSI device and an SoC device have been used in mobile intelligence apparatus and personal computers as information handling equipment, etc. have been recently developed to have high-degree performances and versatile functions. For large scale and high-speed system LSI devices and SoC devices, a technology called the design for testability (DFT), such as a scan-test method and a built-in self-test (BIST) method, is used to prevent test costs, etc. from increasing. In the scan-test method, flip-flop circuits are substituted for scan flip-flop circuits. When the scan flip-flop circuits are used, their values can be set from the outside and such values can be read out from outer input-output terminals of the scan flip-flop circuits. As a result, test patterns can be made easily by means of an automatic test pattern generator (ATPG) as disclosed in Japanese Patent Publication 2002-329784, for instance (see particularly descriptions on page 5 and FIG. 2).
A scan-test circuit used in the scan-test method receives a scan-shift enable signal as a scan control signal. When the scan-shift enable signal is supplied through pipe-lined architecture, additional flip-flop circuits are inserted in the circuits to distribute scan enable signals to loads and to synchronize the same with each other. Such arrangements are so troublesome for timing adjustments and layout design that the arrangements take unexpected time for design and are difficult for optimization.
The present invention provides a scan test circuit with easy optimization for timing adjustments and layout design and a method of arranging the same.